Friday, June 13, 2008

Panning for Gold in California

I'm not sure I actually attended DAC. That root canal flared up and I needed a visit to an emergency dentist the day before flying out in order to pick up some antibiotics to kill off the nascent abscess. That, and heavy doses of Vicodin and ibuprofen left me a bit dazed as I wandered around the exhibits.

Or maybe that was just the exhibits.

Because as the pain, abscess, and Vicodin wore off (and yes, it was just those things - I didn't even make it to the Denali party), I realized just what DAC is (apart from being a Cortical Homunculus). It's another California Gold Rush. True, we're a bit further south than Coloma, but it feels the same. Excited people, from all corners of the globe, descending on an unsuspecting town in the hope of finding a particularly large nugget of value. And, as with the actual Gold Rush, much of the hope is forlorn. It's not that there's no value to be found. Far from it. But the really big nuggets? Like the one found by Spider Conway in "Pale Rider"? Those are rare events.

Finding a major nugget can be industry-changing and create one of those inverted knees in growth curves. Unfortunately, but not unexpectedly, there were none at DAC this year. In fact, in the area of front-end digital VLSI design, I reckon there have really only been two such nuggets found in the last 25 years. The biggest was synthesis of RTL in the early 80's. This was to VLSI design what the then Taniyama-Shimura Conjecture was to Fermat's Last Theorem. Taniyama-Shimura said, very (very) roughly, of two areas of mathematics,
"See elliptic curves? See modular forms? Well, they're kinda the same thing."
As a result, theorems from one area were then able to be applied to the other area, solving problems that had remained pains in the neck for years. And so it was with synthesis in VLSI design. Acting as chip design's very own T-S Conjecture (now a proven Theorem):
"See hardware design? See software design? Well, they're kinda the same thing"
And then all of a sudden, freed from the restrictions of schematic capture, chip designers were able to look to their software cousins and pinch years of well-established methods and norms and apply them to their problems.

The other major nugget was "found" a decade later, in the form of high level hardware verification languages, such as e and Vera. It was more of a corollary to the bigger discovery of synthesis, rather than a significant theorem in its own right. But it was still highly significant. While RTL, expressed in Verilog or VHDL, was a huge advance on schematic capture, it was still little more than assembly code. HVLs raised the abstraction significantly, and were to HDLs, what C, C++ and beyond are to X86 assembler.

But anyway, as I say, no such nuggets this year. There were, however, a fair number of smaller prizes. None will create a revolution, but if each can knock 2% or so off product cycle times, that can soon add up to significant value.

The most obvious has to be the perennial (and my word is it perennial!) Formal Verification. Jasper, One-Spin, Averant, to name but three. FV's biggest problem is probably its associated over-hyped expectations. But keep it in perspective and it's absolutely a Good Thing. Only yesterday, there was a rapid-fire internal mailing list discussion between some of the Verilab teams in the UK, Germany and US about the applicability of FV to a particularly complex arbiter structure. If the time to verify that structure can be reduced from four weeks to one week, with the added benefit of the confidence provided by FV, what's not to like. Just don't get carried away. FV has been touted as The Answer for at least the past ten years, and it will be so touted for years to come. It's not, and it won't be. But not being The Answer doesn't mean it can't be an answer.

Another example is Certess's Certitude. This is trying to deal with the worrying problem that testbenches are becoming at least as complex and, as a result, bug-prone, as the designs they are meant to verify. Given that growth in complexity, how can we be sure that the testbench is able to spot a bug in the design if one exists. In some ways, Certitude is more like a nugget of platinum than one of gold, in the sense that it has been staring us in the face for ages but we haven't noticed its value. I spoke to one of Certess's founders, Mark Hampton, several years ago when they first conceived the idea. It was one of those "Dang, that's so obvious. Why didn't I think of that?" moments. Five years or more on, and clearly putting that "obvious" idea into practice has taken a lot of work. But it looks promising. Again, it's not like inventing the wheel, or discovering penicillin, or realizing that if you stick your finger in a glass of newly-poured diet coke the froth will dissipate more quickly. But worth keeping an eye on nonetheless.

Finally, an at-first-sight uninteresting nugget from Starnet. Their X-Win32 X server is barely noticeable amid the shouts of "OVM!", "VMM!", "My simulator can beat your simulator!" heard all around the DAC exhibition floor. But think about it. VNC-ish-ness, persistence an' all, but faster (if their claims are true). With the increase in use of distributed teams, that could be similar to the sort of performance improvement you get when moving from a 12" monitor to two 22" monitors. A lot. And, at a couple of hundred bucks or less to get those wave displays refreshing faster - not so uninteresting after all.

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