Tuesday, August 26, 2008

Much Ado About Methodologies

ACT 1 Scene 1
It's an an early morning in Verilab Austin. Tommy's office. He's just picked up Davie Robinson who is visiting from the UK Verilab team. Davie's now working in the conference room with JL, while Tommy goes over his email. As he works his way through the list, a sequence of visitors arrive, either physically or via new emails or IMs:

[Davie pops his head through Tommy's office doorway]

So, when did we standardize on the VMM?

When did we what?

The VMM. You said we standardized on it.

[JL arrives next to Davie]

Why did you say we've standardized on the VMM?

[suspicious] Who says I said we standardized on it?

Davie and JL:
[together - pointing to a press release] That did!

Email from Gordon (Verilab UK):
Seems we've standardized on the VMM

Did you see Gordon's email?

Hang on I'm ....

Email from Mark (Verilab Germany):
I'm using OVM at the moment. Am I supposed to stop?

[Exeunt JL and Davie. Backing away, slowly]

Here's the reason for the consternation:


You see, the trouble with press releases, as any political press secretary will tell you, is the devil's in the details but the message is in the large. You have to keep an eye on them both. Here's the core of our quote:
"We have found that VMM can act as a key component in such a deployment [of an effective methodology]..."

And that does indeed reflect the reality of our day to day work. The VMM really can, and in fact does, add significant value to chip teams. We have deployed, are deploying, and will continue to deploy the VMM at clients where it is appropriate. Now as is normal with press releases, that phrase and others went through various revisions, back and forth between us and the final editor.  But in the end, the meaning stayed intact. Now look at the bigger context:

"Leading European Design Consulting Firms Standardize on VMM Verification Methodology"

Unfortunately that can obviously be interpreted as:
"Leading European Design Consulting Firms Standardize EXCLUSIVELY on VMM Verification Methodology"
And of course in Verilab's case, that isn't correct. Here's why.

Verilab tries to plough a scrupulously objective furrow in EDA when it comes to tool vendors. Our primary allegiance is, rather, to our clients. And while we consider Cadence and Mentor and Synopsys (see how they're in mere alphabetical order) among several others to be our good friends and partners, we are exclusive to none of them. And by "objective", we don't mean we'll say the same amount of nice things about each vendor. If vendor A's offerings were consistently inferior to vendor B's for a given client, we'd tell the client (and, if they were open to our advice, the vendor). And if A was consistently worse than B for everyone else; well we may well tell everyone. That's our job. And it's why our clients like us. We're not just contractors, we're consultants. We've seen more chip flows, across more tool suites, in more clients and more countries than most any other team on the planet. And we have no hidden tool agenda. If a spade needs calling a spade, we'll do it. So if the amount of nice (or nasty) things we say about each vendor happens to be the same for each, that's because that's how we call it. And in fact, that *is* in general how we call it. Our view is, consistently, that choice of tool vendor is not, from a technical point of view, the decisive factor in verification capability. Verification is fundamentally a problem of Peopleware; not, per se, Software, or Toolware.

So there you have it. Verilab absolutely believes that the VMM can be a key component in the deployment of an effective verification methodology. But it is not the only such key component and it is not the only approach used by Verilab.

It is, as Shakespeare said, my bad. None of this was the fault of anyone at Synopsys.

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